By Keliu Shu
CMOS PLL Synthesizers: research and Design provides either basics and cutting-edge PLL synthesizer layout and research suggestions. a whole evaluate of either system-level and circuit-level layout and research are lined. A 16mW, 2.4GHz, sub-2V, S D fractional-N synthesizer prototype is applied in 0.35mm CMOS. It encompasses a high-speed and powerful phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which elegantly take on velocity and integration bottlenecks of PLL synthesizer.
This ebook comes in handy as a PLL synthesizer handbook for either educational researchers and layout engineers.
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Extra info for CMOS PLL Synthesizers: Analysis and Design
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6MHz offset is -43dBm, the channel bandwidth is 200kH2, and the required SNR is 9dB. 32), in this offset frequency range, the phase noise and spur level should be less than - 12ldBc/Hz and -68dBc, respectively. Another example is the derivation of phase noise requirement for Bluetooth receiver at 3MHz offset. The out-ofband interference power beyond 3MHz offset is -40dBm, the channel bandwidth is lMHz, the required SNR is 16dB, and the block margin at 3MHz is 6dB. If we want to achieve an input sensitivity of -82dBm (better than the specified -70dBm), the phase noise at 3MHz should be less that -1 24dBdHz.